Ryzen Medusa & Epyc Venice: AMD Zen 6 to use chiplets in N2P and I/O die in N3P

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AMD Zen-6 

AMD Zen-6 architecture will rely on TSMC N2 manufacturing. This was celebrated again recently by both partners for the tape-out. Specifically, it should revolve around the performance-tuned N2P variant. The new I / O-Die does not keep up with this, but still makes an even bigger leap.

Zen 6 and Zen 6c in N2P?

The fact that the CCDs with probably 12 instead of 8 cores for Ryzen and Epyc (Zen 6) for the first time and the Dense CCDs with 32 instead of the previous 16 cores (Zen 6c) for Epyc Dense for the first time are using N2P is not a surprise, at least for Ryzen and Epyc, while Zen 5c is currently using N3E - i.e. the variant trimmed for efficiency instead of performance.

The I/O die in N3P?

Meanwhile, the I / O of the chiplet-Ryzen and Epyc processors would make an even bigger leap. Because according to Kepler_L2 TSMC N3P is used. It is currently being manufactured in an N6 process at TSMC.

AMD Zen 6(c) launches in 2026

According to AMD, the next Zen-6 generation should be launched on the market with Epyc next year. "Venice", also known as Epyc 9006, will once again offer a maximum of 8 chiplets with up to 32 Zen-6 cores and thus a total of up to 256 cores from 2 nm production.

The current Epyc 9005 alias Turin currently offers a maximum of 128 Zen-5 cores with 16 8-core CCD as "Turin Classic" and a maximum of 192 Zen-5c cores with 12 16-core CCDs as "Turin Dense".

Whether new Zen-6-based Ryzen will be released before or after the Epyc processors, there is currently no reliable information available about this yet.