PLC instead of QLC : SK Hynix makes NAND memory cells oval - and thus saves itself a lot of trouble

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Source: SK Hynix 

SK Hynix has introduced a new approach to operating NAND flash memory as a PLC with five bits per cell. This is made possible by an elongated shape with a partition. With this approach, the company avoids previous problems

In order to increase the storage capacity per chip, the individual NAND memory cells could previously simply be made smaller and smaller. However, this development slowed down significantly years ago, so manufacturers are taking other paths. On the one hand, an attempt is being made to stack more and more storage layers on top of each other. On the other hand, more and more bits are accommodated in each cell. Currently, the change from TLC to QLC is taking place here, i.e. from three to four bits per cell. And the densification should continue in the future as well - the manufacturers have long been keeping an eye on PLC with five bits per cell.

Oval and split in two

However, with each additional bit, the number of states that must be distinguished in the cell doubles. With QLC it is still "only" 16, with PLC it would be 32. And thus it is becoming increasingly difficult to measure which value was now stored exactly. SK Hynix is therefore looking for ways to break out of the existing approach. And apparently the company found what it was looking for: a new approach called Multi-Site Cell (MSC) was presented at the IEDM semiconductor trade fair, in which the memory cells are no longer manufactured round, but oval - with 20 percent more length and correspondingly less width.

Storage Technology	Abbreviation	Bits per cell	States per cell
Single-Level Cell	SLC	1	2
Multi-Level Cell	MLC	2	4
Triple-Level Cell	TLC	3	8
Quad-Level Cell	QLC	4	16
Penta-Level Cell	PLC	5	32
Multi-Site Cell (MSC) as PLC	MSC	5	(2•)6

This allows a separating layer to be drawn in, which divides the cell into two parts. Only six states are then stored per segment, which together can map 6 •6 =36 combinations. This, in turn, is enough for PLC - and there are even four pairs left for possible error corrections.

Source: SK Hynix

The old, round structure (left) and the new, oval structure (right).

Microscopic images of the new PLC memory cells. The two-part, elongated structure is clearly visible.

According to SK Hynix, the greater distance achieved in this way between the individual data states of the half-cells should offer several advantages. Among other things, it ensures less interference and can be read out more quickly: supposedly only a maximum of three measurement steps are necessary for this instead of normally seven. This would make the new PLC cells both faster and more efficient. And although it is not explicitly mentioned by the company, it is possible that more states could be stored here per half cell in the future. With eight states, HLC memory with six bits per cell would already be possible.

SK Hynix

By dividing the memory cells into two, larger voltage differences can be used in each half. This allows SK Hynix to circumvent several problems.

SK Hynix

At the dividing point of the oval memory cells, the electrical fields used to control them bend. This presents a new challenge for engineers, as this does not occur with perfectly round memory cells.

However, according to SK Hynix, it is not yet certain whether the new MSC cells will actually prevail: apparently, it is only a possible candidate. Presumably, production is still causing problems at the moment, and other areas such as durability would also have to be examined in detail before mass production. However, the approach is exciting in any case - and it shows that the end has certainly not yet been reached with the current QLC technology.

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