Zen 6: Ryzen X with 24 processor cores and 288 MiB L3 cache
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| Zen 6 |
Once again, exciting rumors are circulating about AMD's upcoming Zen 6 microarchitecture ("Morpheus") and the Ryzen X series desktop processors ("Olympic Ridge") based on it. A true cache monster with 24 Zen 6 cores is expected.
Once again, extremely exciting rumors are now making the rounds about AMD's Zen 6 alias "Morpheus" microarchitecture planned for 2026 and desktop CPUs based on it from the Ryzen X - or Ryzen 10000 - alias "Olympic Ridge" series, which were shared by the usually well-informed HXL (@9550pro). For the readership of PCGH, however, this is not entirely new information, although they go into a little more detail. Already in July 2025 it was speculated that the AMD Ryzen X could become real cache monsters.
Zen 6 Specs: 3D V-Cache should be stacked up to 192 MiBytes
While at that time, based on information from Moore's Law Is Dead, up to 192 MiBytes of 3D V-Cache (2 × 96 MiBytes) and 48 MiBytes of classic L3 cache on the CPU were already running out, HXL (@955pro) is now going a little further. According to this, AMD will also oppose an Intel Core Ultra 9 4XXK with 52 cores or 288 MiByte bLLC ("Big Last Level Cache") with 288 MiBytes. How to do this is quite simple.
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| Zen 6 Ryzen X |
Ryzen X is intended to enable up to 12 Zen-6 processor cores as well as 48 MiBytes of classic L3 cache per CCD ("Core Complex Die"), which are supplemented by 96 MiBytes of 3D V-Cache instead of the previously stacked 64 MiBytes. Since Ryzen X is to be expanded to 24 Zen-6 cores for the processor cores, two CCDs with double L3 cache are used accordingly.
With Zen 6, AMD is supposed to start stacking the 3D V cache in two layers ("2-Hi") for the first time. - Shero King
This means that a Ryzen X with 12 Zen-6 processor cores offers a total of 144 MiByte L3 cache on one CCD, while a model with 24 Zen-6 processing units, on the other hand, launches on two CCDs with 288 MiByte L3 cache. In addition to the 3D V cache, which may be stacked in two layers in the future, the classic L3 cache with Zen 6 is also to grow from the current 32 to 48 MiBytes.
| Ryzen 9000 Ryzen 9000X3D | Ryzen X/10000 Ryzen X3D/10000X3D* | |
|---|---|---|
| Code name | Granite Ridge Granite Ridge-X | Olympic Ridge Olympic Ridge-X |
| microarchitecture | Zen 5 (Nirvana) | Zen 6 (Morpheus) |
| Processor cores per CCD | 6 to 8 | 6 to 12 |
| Total processor cores | 6 to 16 | 6 to 24 |
| L3 cache per CCD | 16 to 32 MiBytes | 24 to 48 MB |
| L3 cache total | 32 to 64 MiByte** | 48 to 96 MiByte** |
| 3D V-Cache | 64 MiByte (1 CCD) | 96 MiByte (1 CCD), 192 MiByte (2 CCD) |
| L3 cache with 3D V-cache | 96 to 128 MiByte*** | 144 MiByte (1 CCD), 288 MiByte (2 CCD)*** |
not officially confirmed. **) without 3D V-Cache. ***) with 3D V-Cache.
In addition, it is speculated that the Ryzen X could have 2 to 4 LPE ("low Power Efficiency") cores based on Zen 5 in addition to their Zen 6 processor cores, depending on the model. However, the manufacturing processes that are implemented at TSMC in 2 nm alias "N2P" for the CCD /CCX and in 3 nm alias "N3P" for the I / O are considered to be the only ones that are secured. Clock frequencies of up to 7 GHz are pure speculation.
The first CPUs based on Zen 6 ("Morpheus") and Zen 6c ("Monarch") could appear late in the 3rd quarter of 2026 and reach the market in larger quantities from the 4th quarter of 2026, according to the current state of information in the rumor mill. Epyc 9006 ("Venice") is expected to make the start, while the processors in the consumer segment will follow at the end of 2026 / beginning of 2027.
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