S: "Vera" CPU also starts independently against AMD Epyc and Intel Xeon

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Source: Nvidia

Nvidia wants to position its "Vera" CPU for data centers as a standalone product without GPUs against Intel's Xeon and AMD's Epyc processors.

The next-gen CPU "Vera" and "Rubin" GPU, which was announced as ready at CES at the beginning of the year, will not only be available as the so-called superchip "Vera Rubin", but also stand-alone for use in data centers. In an interview with Bloomberg, Nvidia CEO Jensen Huang has announced that the processor will also appear as a standalone product, Techpowerup reports, citing Bloomberg tech anchor Ed Ludlow's X channel. According to the report, this marks Nvidia's first entry as a competitor to Intel's Xeon and AMD's Epyc CPUs in the server sector.

As part of a cooperation with the AI cloud provider Coreweave, Huang confirmed as a potential first customer: "For the first time, we will be offering Vera CPUs. Vera is an incredible CPU. We will offer Vera CPUs as an independent part of the infrastructure. You can now run your computing stack not only on Nvidia GPUs, but also on Nvidia CPUs. Vera is absolutely revolutionary." Coreweave must act quickly if it wants to be the first company to implement Vera CPUs," Huang said. "We haven't announced any of our CPU design successes yet, but there will be many."

Background on Nvidia's "Vera" CPU

Nvidia's "Vera" CPU is equipped with 88 custom-made Armv-9.2 "Olympus" cores, which use spatial multithreading technology and are designed to process by physical resource allocation with 176 threads. The cores support native FP8 processing, so some AI workloads can run directly on the CPU with a 6×128-bit SVE2 implementation. The chip also offers a memory bandwidth of 1.2 TB/s and supports up to 1.5 TiB of LPDDR5X memory, making it ideal for memory-intensive computing tasks.

However, since the CPU is now offered as a standalone solution, it is unclear, according to the report, whether there are classic memory options such as DDR5-RDIMMs or whether the CPU will rely exclusively on SOCAMM-LPDDR5X. Meanwhile, a scalable coherence structure of the second generation should have a bisection bandwidth of 3.4 TB / s, connects the cores via a uniform monolithic chip and should thus eliminate the latency problems common in chiplet architectures. In addition, with NVLink, Nvidia has integrated its second-generation chip-to-chip technology, which provides a coherent bandwidth of up to 1.8 TB/s for external "ruby" GPUs.

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